GF will be responsible for the following tasks:
● Design of required electronic circuits to build demonstrator described in WP5 work package in two phases.
● In phase 1, Simulation and design of 56Gb/s NRZ driver for Electro absorption modulator and transimpedance amplifier with sufficient bandwidth to support 56Gb/s transmission.
● In the second design iteration the objective is to push the bandwidth of the TIA and modulation speed of the driver to maximum of the 22FDX technology, targeting 112Gb/s NRZ transmission speed.
● Fabrication of EIC chips in 2 MPW runs and providing diced samples to imec for assembly of EIC-PIC demonstrators